1. Field of the Invention
The present invention relates to a non-volatile memory, and more particularly, to a NAND-type non-volatile memory.
2. Description of the Prior Art
A flash memory belongs to a non-volatile memory and has an important characteristic of storing data in the memory even though the power is turned off. In addition, having a high operation speed for repeated read, program and erase is also important for the flash memory to be widely used and rapidly developed. The flash memory can be divided according to structure into NOR flash memory and NAND flash memory. The drains of memory cells of a NOR flash memory are connected in parallel for a faster reading speed, which is suitable for code flash memory mainly used for executing program code. The drains and sources of two neighboring memory cells of a NAND flash memory are serially connected for integrating more memory cells per unit area, which is suitable for a data flash memory mainly used for data storage. Both NOR flash memory and NAND flash memory have a MOS-like memory cell structure, so as to provide advantages of small size, high operation speed and high density.
Referring to FIG. 1, FIG. 1 is a cross-sectional diagram of a flash memory according to the prior art. As shown in FIG. 1, a flash memory 10 has a substrate 12, a P well 14 formed in the substrate 12, a plurality of N-type doping regions 16 formed in the P well 14, and a plurality of stacked structures composed of an oxide layer 18, a floating gate 20, an oxide layer 22, and a control gate 24 formed on the substrate 12.
Each of the N-type doping regions 16 is used to define a buried drain/source (BD/BS), and a channel region L is defined between two neighboring N-type doping regions 16. In the manufacturing processes, the oxide layer 18, the floating gate 20, the oxide layer 22, and the control gate 24 are respectively formed and patterned on the surface of the P well 14, and thereafter, the N-type doping regions are formed using a doping process to dope N-type ions into a predetermined region of the P well 14, and using a thermal process to activate and diffuse the N-type ions so as to complete the profiles of the N-type doping regions 16 and the channel regions L. During the thermal process, however, the N-type ions doped into the P well 14 can be laterally diffused to shorten a length of the channel region L. To ensure the channel length satisfying specific device characteristics, a conventional method is used to increase the line widths of the stacked structures, including the control gate 24, so as to increase the distance between two neighboring N-type doping regions 16 to reserve enough space for the thermal diffusion. While the distance between two neighboring N-type doping regions 16 is increased, a feature size of the memory cell is also increased. Therefore, how to consider a tradeoff between the channel length and the thermal budget so as to obtain satisfying device characteristics without sacrificing the cell size becomes an important issue.